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serdes

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Published By: Mentor Graphics     Published Date: Apr 03, 2009
For advanced signaling over high-loss channels, designs today are using equalization and several new measurement methods to evaluate the performance of the link. Both simulation and measurement tools support equalization and the new measurement methods, but correlation of results throughout the design flow is unclear. In this paper a high performance equalizing serial data link is measured and the performance is compared to that predicted by simulation. Then, the differences between simulation and measurements are discussed as well as methods to correlate the two.
Tags : 
mentor graphics, equalized serial data links, design flow, high loss channels, tektronix, pcb, bit error rate, ber
    
Mentor Graphics
Published By: Mentor Graphics     Published Date: Apr 25, 2016
Over the years, two major approaches to SERDES simulation have emerged and gained popularity: time-domain (or bit-by-bit) and statistical. Both are used to build the eye diagram and bit-error ratio (BER), and each has its benefits and limitations.
Tags : 
mentor graphics, analysis flow, bit by bit, serdes, ber, gigabit networking, internetworking hardware
    
Mentor Graphics
Published By: Mentor Graphics     Published Date: Oct 08, 2014
This paper reports on common layout requirements related to SERDES designs, and how HyperLynx DRC can help identify issues on PCB boards that violate these requirements.
Tags : 
mentor graphics, boards, serdes, pcb boards, drc, gigabit networking, internetworking hardware, power and cooling
    
Mentor Graphics
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